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S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
March. 2000. Ver. 1.0
Prepared by:
Myoung-Sik, Suh mail to: mssuh@samsung.co.kr
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670 Specification Revision History Version 0.0 1.0 Original "Resistor strings" , "CLK1 pulse high period" Content Date Aug.1999 Mar.2000
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8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
CONTENTS
INTRODUCTION ................................................................................................................................................. 4 FEATURES ......................................................................................................................................................... 4 BLOCK DIAGRAM .............................................................................................................................................. 5 PIN ASSIGNMENTS............................................................................................................................................ 6 PIN DESCRIPTIONS........................................................................................................................................... 7 OPERATION DESCRIPTION .............................................................................................................................. 8 DISPLAY DATA TRANSFER............................................................................................................................ 8 EXTENSION OF OUTPUT ............................................................................................................................... 8 RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE................................................. 8 RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE............................................... 12 ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 26 RECOMMENDED OPERATION CONDITIONS ................................................................................................. 26 DC CHARACTERISTICS................................................................................................................................... 27 SINGLE EDGE AC CHARACTERISTICS.......................................................................................................... 28 DOUBLE EDGE AC CHARACTERISTICS ........................................................................................................ 29 SINGLE EDGE WAVEFORMS (VIH = 0.8 VDD1, VIL = 0.2 VDD1) ................................................................... 30 DOUBLE EDGE WAVEFORMS (VIH = 0.8 VDD1, VIL = 0.2 VDD1).................................................................. 31 RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD....................... 32
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S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
INTRODUCTION
The S6C0670 is a 384 / 402 channel output, TFT-LCD source driver for an 256 gray scale LCD panel. Data input is based on digital input consisting of 8 bits by 6 dots, which can realize a full-color display of 16,700,000 color by output of 256 values gamma-corrected. This device has an internal D/A (Digital-to-Analog) converter for each output and 16 (8-by-2) reference voltages. Because the output dynamic range is as large as 7.8 - 14.8 Vp-p, it is unnecessary to operate level inversion of the LCD's common electrode. Besides, to be able to deal with dot-line inversion when mounted on a single-side, output gray scale voltages with different polarity can be output to the odd number output pins and the even output pins. S6C0670 can be adopted to larger panel, and SHL (shift direction selection) pin makes the use of the LCD panel connection conveniently. Maximum operation clock frequency is 75 MHz at 3.0 V logic operation, single edge and it can be applied to the TFT-LCD panel of UXGA standard.
FEATURES
* * * * * * * * * * * * * TFT active matrix LCD source driver LSI 256 G/S is possible through 16 (8 by 2) reference voltages and D/A converter Both dot inversion display and N-line inversion display are possible CMOS level input Compatible with gamma-correction Input data inversion function (DATPOL1,2) Single edge, Double edge compatible (DEC) Logic supply voltage: 2.5 - 3.6 V LCD driver supply voltage: 8.0 - 15.0 V Output dynamic range: 7.8 - 14.8 Vp-p Maximum operating frequency: fMAX = 75 MHz (internal data transmission rate at 3.0 V operation, single edge) Output: 384 / 402 outputs TCP available
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8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
BLOCK DIAGRAM
Y402 Y401 Y400 Y003 Y002 8 8 Y001 8 8
Output Buffer
POL VGMA1 VGMA16
16
D/A Converter
8
8
8
8
CLK1
Data Latch
8
8
8
8
DATPOL1 DATPOL2 D00 - D07 D10 - D17 D20 - D27 D30 - D37 D40 - D47 D50 - D57 8 Data Control 8 8 8 8 8 24 24
Data Register
67bit Shift Register
CLK2
DIO2
SHL
SELT
DEC
DIO1
Figure 1. S6C0670 Block Diagram
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S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
PIN ASSIGNMENTS
DIO1 D00 D01 D02 D03 D04 D05 D06 D07 D10 D11 D12 D13 D14 D15 D16 D17 D20 D21 D22 D23 D24 D25 D26 D27 TEST DATPOL1 DATPOL2 POL CLK1 CLK2 DEC VSS1 VGMA1 VGMA2 VGMA3 VGMA4 VGMA5 VGMA6 VGMA7 VGMA8 VSS2 VDD2 VGMA9 VGMA10 VGMA11 VGMA12 VGMA13 VGMA14 VGMA15 VGMA16 SELT SHL VDD1 D30 D31 D32 D33 D34 D35 D36 D37 D40 D41 D42 D43 D44 D45 D46 D47 D50 D51 D52 D53 D54 D55 D56 D57 DIO2
Y001 Y002 Y003 Y004
S6C0670
Y399 Y400 Y401 Y402 6
Figure 2. S6C0670 Pin Assignments
(Top View)
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
PIN DESCRIPTIONS
Description 2.5 - 3.6 V 8.0 - 15.0 V Ground (0 V) Ground (0 V) The D/A converted 256 gray-scale analog voltage is output. The display data is input with a width of 48 bits, Display data input gray-scale data (8 bits) by 6 dots (R,G,B) DX0: LSB, DX7: MSB This pin controls the direction of shift register in cascade connection. Shift direction control The shift direction of the shift registers is as follows. SHL input SHL = H: DIO1 input, Y1 Y402, DIO2 output SHL = L: DIO2 input, Y402 Y1, DIO1 output SHL = H: Used as the start pulse input pin. DIO1 Start pulse input/output SHL = L: Used as the start pulse output pin. SHL = H: Used as the start pulse output pin. DIO2 Start pulse input/output SHL = L: Used as the start pulse input pin. DATPOL1,2 = L: Display data is not inverted DATPOL1 Data inversion input DATPOL1 = H: Display data of D0<0:7> - D2<0:7> is inverted DATPOL2 DATPOL2 = H: Display data of D3<0:7> - D5<0:7> is inverted POL = H: The reference voltage for odd number outputs are VGMA9 - VGMA16 and those for even number outputs are VGMA1 - VGMA8. POL Polarity input POL = L: The reference voltage for odd number outputs are VGMA1 - VGMA8 and those for even number outputs are VGMA9 - VGMA16. Refer to the shift register's shift clock input. When DEC is Low, the display data is loaded to the data register at the rising edge of CLK2 Shift clock input CLK2.When DEC is High, the display data is loaded to the data register at the rising and falling edge of CLK2. Latches the contents of the data register at rising edge and transfers them to the D/A converter. Also, after CLK1 input, clears the internal shift register contents. After 1 pulse input on start, operates normally. CLK1 Latch input CLK1 input timing refers to the "Relationships between CLK1 start pulse (DIO1, DIO2) and blanking period" of the switching characteristic waveform. Outputs the G/S data at falling edge. Input the gamma corrected power supplies from external source. VGMA1 Gamma corrected power VDD2 > VGMA1 > VGMA2 > ...... > VGMA15 > VGMA16 > VSS2 - supplies Keep gray-scale power supply unchanged during the gray-scale VGMA16 voltage output. SELT = L: 384 Output (Y193 - Y210 are disabled), SELT = H: 402 SELT Output selection input Output DEC = L: Single Edge, the display data is loaded to the data register at Double edge selection DEC the rising edge of CLK2. DEC = H: Double Edge, the display data is input loaded to the data register at the rising and falling edge of CLK2. TEST = L: Normal operation mode TEST Test input TEST = H: Test mode (OP AMP CUT-OFF, Rpd = 10k) Symbol VDD1 VDD2 VSS1 VSS2 Y1 - Y402 D0<0:7> - D5<0:7> Pin Name Logic power supply Driver power supply Logic ground Driver ground Driver outputs
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S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
OPERATION DESCRIPTION
DISPLAY DATA TRANSFER
(1) DEC = "L" When DIO1 (or DIO2) pulse is loaded into internal latch on the rising edge of CLK2, DIO1 (or DIO2) pulse enables the operation of data transfer, so display data is valid on the next rising edge of CLK2. Once all the data of 402 (or 384) channels is loaded into internal latch, it goes into stand-by state automatically, and any new data is not accepted even though CLK2 is provided until next DIO1 (or DIO2) input. When next DIO1 (or DIO2) is provided, new display data is valid on the 2nd rising edge of CLK2 after the rising edge of DIO1 (or DIO2). (2) DEC = "H" When DIO1 (or DIO2) pulse is loaded into internal latch on the rising (or falling) edge of CLK2, DIO1 (or DIO2) pulse enables the operation of data transfer. display data is valid on the next falling (or rising) edge of CLK2. Once all the data of 402 (or 384) channels is loaded into internal latch, it goes into stand-by state automatically, and any new data is not accepted even though CLK2 is provided until next DIO1 (or DIO2) input. When next DIO1 (or DIO2) is provided, new display data is valid on the 2nd edge of CLK2 after the rising edge of DIO1 (or DIO2).
EXTENSION OF OUTPUT
Output pin can be adjusted to an extended screen by cascade connection. (1) SHL = "L" Connect DIO1 pin of previous stage to the DIO2 pin of next stage and all the input pins except DIO1 and DIO2 are connected together in each device. (2) SHL = "H" Connect DIO2 pin of previous stage to the DIO1 pin of next stage and all the input pins except DIO2 and DIO1 are connected together in each device.
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE
The LCD drive output voltages are determined by the input data and 16 (8 by 2) gamma corrected power supplies (VGMA1 - VGMA16). Besides, to be able to deal with dot line inversion when mounted on a single-side, gradation voltages with different polarity can be output to the odd number output pins and the even number output pins. Among 8-by-2 gamma corrected voltages, input gray-scale voltages of the same polarity with respect to the common voltage, for the respective 8 gamma corrected voltages of VGMA1 - VGMA8 and VGMA9 - VGMA16.
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8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
SHL = H
OUTPUT DATA D00 - D07 Y1 Y2 First D10 - D17 D20 - D27 ...... D30 - D37 Y3 ...... Y400 Y401 Last D40 - D47 D50 - D57 Y402
SHL = L
OUTPUT DATA D00 - D07 Y1 Y2 Last D10 - D17 D20 - D27 ...... D30 - D37 Y3 ...... Y400 Y401 First D40 - D47 D50 - D57 Y402
Figure 3. Relationship between Shift Direction and Output Data
VDD2 VGMA1
32
VGMA2 VGMA3 VGMA4 VGMA5 VGMA6
32 64 64 48
14
VGMA7,8 VGMA9,10
VCOM
14
VGMA11
48
VGMA12 VGMA13 VGMA14 VGMA15 VGMA16 VSS2 00H 20H 40H 60H 80H A0H C0H E0H FFH
64 64 32 32
Figure 4. Gamma Correction Curve
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S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
Table 1. Resistor Strings (R0 - R254, unit: ) Name R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 Value 404 320 263 224 196 177 163 153 144 138 132 127 122 118 113 109 106 102 99 96 93 90 88 86 84 82 80 79 77 76 75 74 Name R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R15 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 Value 74 73 72 72 71 71 71 70 70 69 69 69 68 68 67 67 66 65 65 64 63 62 61 60 59 58 57 56 55 53 52 51 Name R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R93 R94 R95 Value 50 49 48 47 46 45 44 43 42 41 40 40 39 38 38 37 37 37 36 36 36 36 36 36 36 36 36 36 36 36 36 36 Name R96 R97 R98 R99 R100 R101 R102 R103 R104 R105 R106 R107 R108 R109 R110 R111 R112 R113 R114 R115 R116 R117 R118 R119 R120 R121 R122 R123 R124 R125 R126 R127 Value 36 36 36 36 36 36 36 36 36 36 35 35 35 35 35 35 35 35 35 34 34 34 34 34 34 34 34 34 34 33 33 33
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8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
Table 1. Resistor Strings (R0 - R254, unit: ) (Continued) Name R128 R129 R130 R131 R132 R133 R134 R135 R136 R137 R138 R139 R140 R141 R142 R143 R144 R145 R146 R147 R148 R149 R150 R151 R152 R153 R154 R155 R156 R157 R158 R159 Value 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 Name R160 R161 R162 R163 R164 R165 R166 R167 R168 R169 R170 R171 R172 R173 R174 R175 R176 R177 R178 R179 R180 R181 R182 R183 R184 R185 R186 R187 R188 R189 R190 R191 Value 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 34 34 34 34 35 35 35 36 36 36 37 37 38 38 Name R192 R193 R194 R195 R196 R197 R198 R199 R200 R201 R202 R203 R204 R205 R206 R207 R208 R209 R210 R211 R212 R213 R214 R215 R216 R217 R218 R219 R220 R221 R222 R223 Value 38 39 39 39 40 40 40 41 41 41 42 42 42 42 43 43 43 43 44 44 45 45 46 47 48 49 51 52 54 56 59 62 Name R224 R225 R226 R227 R228 R229 R230 R231 R232 R233 R234 R235 R236 R237 R238 R239 R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 Value 65 69 73 77 82 87 92 97 103 109 115 122 128 134 141 147 154 161 168 177 187 199 215 238 270 318 396 533 811 817 831
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S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
Table 2. Relationship between Input Data and Output Voltage Value (1) Input data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G/S VH0 VH1 VH2 VH3 VH4 VH5 VH6 VH7 VH8 VH9 VH10 VH11 VH12 VH13 VH14 VH15 VH16 VH17 VH18 VH19 VH20 VH21 VH22 VH23 VH24 VH25 VH26 VH27 VH28 VH29 VH30 VH31 VH32 VH33 VH34 VH35 VH36 VH37 VH38 VH39 Output voltage VGMA1 VGMA1 + (VGMA2 - VGMA1) x 404 / 4288 VGMA1 + (VGMA2 - VGMA1) x 724 / 4288 VGMA1 + (VGMA2 - VGMA1) x 987 / 4288 VGMA1 + (VGMA2 - VGMA1) x 1211 / 4288 VGMA1 + (VGMA2 - VGMA1) x 1408 / 4288 VGMA1 + (VGMA2 - VGMA1) x 1585 / 4288 VGMA1 + (VGMA2 - VGMA1) x 1748 / 4288 VGMA1 + (VGMA2 - VGMA1) x 1900 / 4288 VGMA1 + (VGMA2 - VGMA1) x 2044 / 4288 VGMA1 + (VGMA2 - VGMA1) x 2182 / 4288 VGMA1 + (VGMA2 - VGMA1) x 2314 / 4288 VGMA1 + (VGMA2 - VGMA1) x 2441 / 4288 VGMA1 + (VGMA2 - VGMA1) x 2562 / 4288 VGMA1 + (VGMA2 - VGMA1) x 2680 / 4288 VGMA1 + (VGMA2 - VGMA1) x 2793 / 4288 VGMA1 + (VGMA2 - VGMA1) x 2903 / 4288 VGMA1 + (VGMA2 - VGMA1) x 3008 / 4288 VGMA1 + (VGMA2 - VGMA1) x 3110 / 4288 VGMA1 + (VGMA2 - VGMA1) x 3209 / 4288 VGMA1 + (VGMA2 - VGMA1) x 3305 / 4288 VGMA1 + (VGMA2 - VGMA1) x 3398 / 4288 VGMA1 + (VGMA2 - VGMA1) x 3488 / 4288 VGMA1 + (VGMA2 - VGMA1) x 3576 / 4288 VGMA1 + (VGMA2 - VGMA1) x 3661 / 4288 VGMA1 + (VGMA2 - VGMA1) x 3745 / 4288 VGMA1 + (VGMA2 - VGMA1) x 3826 / 4288 VGMA1 + (VGMA2 - VGMA1) x 3906 / 4288 VGMA1 + (VGMA2 - VGMA1) x 3985 / 4288 VGMA1 + (VGMA2 - VGMA1) x 4062 / 4288 VGMA1 + (VGMA2 - VGMA1) x 4138 / 4288 VGMA1 + (VGMA2 - VGMA1) x 4214 / 4288 VGMA2 VGMA2 + (VGMA3 - VGMA2) x 74 / 2065 VGMA2 + (VGMA3 - VGMA2) x 147 / 2065 VGMA2 + (VGMA3 - VGMA2) x 219 / 2065 VGMA2 + (VGMA3 - VGMA2) x 291 / 2065 VGMA2 + (VGMA3 - VGMA2) x 362 / 2065 VGMA2 + (VGMA3 - VGMA2) x 433 / 2065 VGMA2 + (VGMA3 - VGMA2) x 504 / 2065
NOTE: VDD2>VGMA1>VGMA2>VGMA3>VGMA4>VGMA5>VGMA6>VGMA7>VGMA8
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8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
Table 2. Relationship between Input Data and Output Voltage Value (2) Input data 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G/S VH40 VH41 VH42 VH43 VH44 VH45 VH46 VH47 VH48 VH49 VH50 VH51 VH52 VH53 VH54 VH55 VH56 VH57 VH58 VH59 VH60 VH61 VH62 VH63 VH64 VH65 VH66 VH67 VH68 VH69 VH70 VH71 VH72 VH73 VH74 VH75 VH76 VH77 VH78 VH79 Output voltage VGMA2 + (VGMA3 - VGMA2) x 574 / 2065 VGMA2 + (VGMA3 - VGMA2) x 644 / 2065 VGMA2 + (VGMA3 - VGMA2) x 713 / 2065 VGMA2 + (VGMA3 - VGMA2) x 782 / 2065 VGMA2 + (VGMA3 - VGMA2) x 851 / 2065 VGMA2 + (VGMA3 - VGMA2) x 919 / 2065 VGMA2 + (VGMA3 - VGMA2) x 987 / 2065 VGMA2 + (VGMA3 - VGMA2) x 1054 / 2065 VGMA2 + (VGMA3 - VGMA2) x 1120 / 2065 VGMA2 + (VGMA3 - VGMA2) x 1186 / 2065 VGMA2 + (VGMA3 - VGMA2) x 1251 / 2065 VGMA2 + (VGMA3 - VGMA2) x 1316 / 2065 VGMA2 + (VGMA3 - VGMA2) x 1380 / 2065 VGMA2 + (VGMA3 - VGMA2) x 1442 / 2065 VGMA2 + (VGMA3 - VGMA2) x 1504 / 2065 VGMA2 + (VGMA3 - VGMA2) x 1565 / 2065 VGMA2 + (VGMA3 - VGMA2) x 1625 / 2065 VGMA2 + (VGMA3 - VGMA2) x 1684 / 2065 VGMA2 + (VGMA3 - VGMA2) x 1742 / 2065 VGMA2 + (VGMA3 - VGMA2) x 1799 / 2065 VGMA2 + (VGMA3 - VGMA2) x 1854 / 2065 VGMA2 + (VGMA3 - VGMA2) x 1909 / 2065 VGMA2 + (VGMA3 - VGMA2) x 1962 / 2065 VGMA2 + (VGMA3 - VGMA2) x 2014 / 2065 VGMA3 VGMA3 + (VGMA4 - VGMA3) x 50 / 2368 VGMA3 + (VGMA4 - VGMA3) x 99 / 2368 VGMA3 + (VGMA4 - VGMA3) x 146 / 2368 VGMA3 + (VGMA4 - VGMA3) x 193 / 2368 VGMA3 + (VGMA4 - VGMA3) x 238 / 2368 VGMA3 + (VGMA4 - VGMA3) x 283 / 2368 VGMA3 + (VGMA4 - VGMA3) x 326 / 2368 VGMA3 + (VGMA4 - VGMA3) x 369 / 2368 VGMA3 + (VGMA4 - VGMA3) x 411 / 2368 VGMA3 + (VGMA4 - VGMA3) x 452 / 2368 VGMA3 + (VGMA4 - VGMA3) x 492 / 2368 VGMA3 + (VGMA4 - VGMA3) x 532 / 2368 VGMA3 + (VGMA4 - VGMA3) x 571 / 2368 VGMA3 + (VGMA4 - VGMA3) x 609 / 2368 VGMA3 + (VGMA4 - VGMA3) x 647 / 2368
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S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (3) Input data 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G/S VH80 VH81 VH82 VH83 VH84 VH85 VH86 VH87 VH88 VH89 VH90 VH91 VH92 VH93 VH94 VH95 VH96 VH97 VH98 VH99 VH100 VH101 VH102 VH103 VH104 VH105 VH106 VH107 VH108 VH109 VH110 VH111 VH112 VH113 VH114 VH115 VH116 VH117 VH118 VH119 Output voltage VGMA3 + (VGMA4 - VGMA3) x 684 / 2368 VGMA3 + (VGMA4 - VGMA3) x 722 / 2368 VGMA3 + (VGMA4 - VGMA3) x 758 / 2368 VGMA3 + (VGMA4 - VGMA3) x 795 / 2368 VGMA3 + (VGMA4 - VGMA3) x 831 / 2368 VGMA3 + (VGMA4 - VGMA3) x 867 / 2368 VGMA3 + (VGMA4 - VGMA3) x 903 / 2368 VGMA3 + (VGMA4 - VGMA3) x 938 / 2368 VGMA3 + (VGMA4 - VGMA3) x 974 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1009 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1045 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1080 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1116 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1151 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1187 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1222 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1258 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1294 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1329 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1365 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1401 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1436 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1472 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1507 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1543 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1579 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1614 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1649 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1685 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1720 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1755 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1790 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1825 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1860 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1895 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1929 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1964 / 2368 VGMA3 + (VGMA4 - VGMA3) x 1998 / 2368 VGMA3 + (VGMA4 - VGMA3) x 2032 / 2368 VGMA3 + (VGMA4 - VGMA3) x 2066 / 2368
14
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
Table 2. Relationship between Input Data and Output Voltage Value (4) Input data 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H 91H 92H 93H 94H 95H 96H 97H 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G/S VH120 VH121 VH122 VH123 VH124 VH125 VH126 VH127 VH128 VH129 VH130 VH131 VH132 VH133 VH134 VH135 VH136 VH137 VH138 VH139 VH140 VH141 VH142 VH143 VH144 VH145 VH146 VH147 VH148 VH149 VH150 VH151 VH152 VH153 VH154 VH155 VH156 VH157 VH158 VH159 Output voltage VGMA3 + (VGMA4 - VGMA3) x 2100 / 2368 VGMA3 + (VGMA4 - VGMA3) x 2134 / 2368 VGMA3 + (VGMA4 - VGMA3) x 2168 / 2368 VGMA3 + (VGMA4 - VGMA3) x 2201 / 2368 VGMA3 + (VGMA4 - VGMA3) x 2235 / 2368 VGMA3 + (VGMA4 - VGMA3) x 2268 / 2368 VGMA3 + (VGMA4 - VGMA3) x 2302 / 2368 VGMA3 + (VGMA4 - VGMA3) x 2335 / 2368 VGMA4 VGMA4 + (VGMA5 - VGMA4) x 33 / 2149 VGMA4 + (VGMA5 - VGMA4) x 66 / 2149 VGMA4 + (VGMA5 - VGMA4) x 100 / 2149 VGMA4 + (VGMA5 - VGMA4) x 133 / 2149 VGMA4 + (VGMA5 - VGMA4) x 166 / 2149 VGMA4 + (VGMA5 - VGMA4) x 199 / 2149 VGMA4 + (VGMA5 - VGMA4) x 232 / 2149 VGMA4 + (VGMA5 - VGMA4) x 266 / 2149 VGMA4 + (VGMA5 - VGMA4) x 299 / 2149 VGMA4 + (VGMA5 - VGMA4) x 332 / 2149 VGMA4 + (VGMA5 - VGMA4) x 365 / 2149 VGMA4 + (VGMA5 - VGMA4) x 399 / 2149 VGMA4 + (VGMA5 - VGMA4) x 432 / 2149 VGMA4 + (VGMA5 - VGMA4) x 465 / 2149 VGMA4 + (VGMA5 - VGMA4) x 498 / 2149 VGMA4 + (VGMA5 - VGMA4) x 532 / 2149 VGMA4 + (VGMA5 - VGMA4) x 565 / 2149 VGMA4 + (VGMA5 - VGMA4) x 598 / 2149 VGMA4 + (VGMA5 - VGMA4) x 632 / 2149 VGMA4 + (VGMA5 - VGMA4) x 665 / 2149 VGMA4 + (VGMA5 - VGMA4) x 698 / 2149 VGMA4 + (VGMA5 - VGMA4) x 732 / 2149 VGMA4 + (VGMA5 - VGMA4) x 765 / 2149 VGMA4 + (VGMA5 - VGMA4) x 798 / 2149 VGMA4 + (VGMA5 - VGMA4) x 831 / 2149 VGMA4 + (VGMA5 - VGMA4) x 864 / 2149 VGMA4 + (VGMA5 - VGMA4) x 897 / 2149 VGMA4 + (VGMA5 - VGMA4) x 930 / 2149 VGMA4 + (VGMA5 - VGMA4) x 963 / 2149 VGMA4 + (VGMA5 - VGMA4) x 996 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1029 / 2149
15
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8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (5) Input data A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H C1H C2H C3H C4H C5H C6H C7H DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G/S VH160 VH161 VH162 VH163 VH164 VH165 VH166 VH167 VH168 VH169 VH170 VH171 VH172 VH173 VH174 VH175 VH176 VH177 VH178 VH179 VH180 VH181 VH182 VH183 VH184 VH185 VH186 VH187 VH188 VH189 VH190 VH191 VH192 VH193 VH194 VH195 VH196 VH197 VH198 VH199 Output voltage VGMA4 + (VGMA5 - VGMA4) x 1062 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1094 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1127 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1159 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1192 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1224 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1257 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1289 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1322 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1354 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1387 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1419 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1452 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1485 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1517 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1550 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1583 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1617 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1650 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1684 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1717 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1752 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1786 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1821 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1856 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1891 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1927 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1963 / 2149 VGMA4 + (VGMA5 - VGMA4) x 1999 / 2149 VGMA4 + (VGMA5 - VGMA4) x 2036 / 2149 VGMA4 + (VGMA5 - VGMA4) x 2073 / 2149 VGMA4 + (VGMA5 - VGMA4) x 2111 / 2149 VGMA5 VGMA5 + (VGMA6 - VGMA5) x 38 / 3080 VGMA5 + (VGMA6 - VGMA5) x 77 / 3080 VGMA5 + (VGMA6 - VGMA5) x 116 / 3080 VGMA5 + (VGMA6 - VGMA5) x 155 / 3080 VGMA5 + (VGMA6 - VGMA5) x 195 / 3080 VGMA5 + (VGMA6 - VGMA5) x 235 / 3080 VGMA5 + (VGMA6 - VGMA5) x 276 / 3080
16
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Table 2. Relationship between Input Data and Output Voltage Value (6) Input data C8H C9H CAH CBH CCH CDH CEH CFH D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G/S VH200 VH201 VH202 VH203 VH204 VH205 VH206 VH207 VH208 VH209 VH210 VH211 VH212 VH213 VH214 VH215 VH216 VH217 VH218 VH219 VH220 VH221 VH222 VH223 VH224 VH225 VH226 VH227 VH228 VH229 VH230 VH231 VH232 VH233 VH234 VH235 VH236 VH237 VH238 VH239 Output voltage VGMA5 + (VGMA6 - VGMA5) x 316 / 3080 VGMA5 + (VGMA6 - VGMA5) x 357 / 3080 VGMA5 + (VGMA6 - VGMA5) x 399 / 3080 VGMA5 + (VGMA6 - VGMA5) x 440 / 3080 VGMA5 + (VGMA6 - VGMA5) x 482 / 3080 VGMA5 + (VGMA6 - VGMA5) x 524 / 3080 VGMA5 + (VGMA6 - VGMA5) x 566 / 3080 VGMA5 + (VGMA6 - VGMA5) x 609 / 3080 VGMA5 + (VGMA6 - VGMA5) x 651 / 3080 VGMA5 + (VGMA6 - VGMA5) x 694 / 3080 VGMA5 + (VGMA6 - VGMA5) x 738 / 3080 VGMA5 + (VGMA6 - VGMA5) x 782 / 3080 VGMA5 + (VGMA6 - VGMA5) x 826 / 3080 VGMA5 + (VGMA6 - VGMA5) x 871 / 3080 VGMA5 + (VGMA6 - VGMA5) x 916 / 3080 VGMA5 + (VGMA6 - VGMA5) x 962 / 3080 VGMA5 + (VGMA6 - VGMA5) x 1009 / 3080 VGMA5 + (VGMA6 - VGMA5) x 1057 / 3080 VGMA5 + (VGMA6 - VGMA5) x 1106 / 3080 VGMA5 + (VGMA6 - VGMA5) x 1157 / 3080 VGMA5 + (VGMA6 - VGMA5) x 1209 / 3080 VGMA5 + (VGMA6 - VGMA5) x 1263 / 3080 VGMA5 + (VGMA6 - VGMA5) x 1320 / 3080 VGMA5 + (VGMA6 - VGMA5) x 1379 / 3080 VGMA5 + (VGMA6 - VGMA5) x 1441 / 3080 VGMA5 + (VGMA6 - VGMA5) x 1506 / 3080 VGMA5 + (VGMA6 - VGMA5) x 1574 / 3080 VGMA5 + (VGMA6 - VGMA5) x 1647 / 3080 VGMA5 + (VGMA6 - VGMA5) x 1724 / 3080 VGMA5 + (VGMA6 - VGMA5) x 1805 / 3080 VGMA5 + (VGMA6 - VGMA5) x 1892 / 3080 VGMA5 + (VGMA6 - VGMA5) x 1983 / 3080 VGMA5 + (VGMA6 - VGMA5) x 2081 / 3080 VGMA5 + (VGMA6 - VGMA5) x 2184 / 3080 VGMA5 + (VGMA6 - VGMA5) x 2293 / 3080 VGMA5 + (VGMA6 - VGMA5) x 2409 / 3080 VGMA5 + (VGMA6 - VGMA5) x 2530 / 3080 VGMA5 + (VGMA6 - VGMA5) x 2658 / 3080 VGMA5 + (VGMA6 - VGMA5) x 2792 / 3080 VGMA5 + (VGMA6 - VGMA5) x 2933 / 3080
17
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8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (7) Input data F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G/S VH240 VH241 VH242 VH243 VH244 VH245 VH246 VH247 VH248 VH249 VH250 VH251 VH252 VH253 VH254 VH255 Output voltage VGMA6 VGMA6 + (VGMA7 - VGMA6) x 154 / 4641 VGMA6 + (VGMA7 - VGMA6) x 314 / 4641 VGMA6 + (VGMA7 - VGMA6) x 482 / 4641 VGMA6 + (VGMA7 - VGMA6) x 659 / 4641 VGMA6 + (VGMA7 - VGMA6) x 846 / 4641 VGMA6 + (VGMA7 - VGMA6) x 1045 / 4641 VGMA6 + (VGMA7 - VGMA6) x 1260 / 4641 VGMA6 + (VGMA7 - VGMA6) x 1498 / 4641 VGMA6 + (VGMA7 - VGMA6) x 1768 / 4641 VGMA6 + (VGMA7 - VGMA6) x 2086 / 4641 VGMA6 + (VGMA7 - VGMA6) x 2482 / 4641 VGMA6 + (VGMA7 - VGMA6) x 3014 / 4641 VGMA6 + (VGMA7 - VGMA6) x 3825 / 4641 VGMA7 VGMA8
18
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
Table 2. Relationship between Input Data and Output Voltage Value (8) Input data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G/S VL0 VL1 VL2 VL3 VL4 VL5 VL6 VL7 VL8 VL9 VL10 VL11 VL12 VL13 VL14 VL15 VL16 VL17 VL18 VL19 VL20 VL21 VL22 VL23 VL24 VL25 VL26 VL27 VL28 VL29 VL30 VL31 VL32 VL33 VL34 VL35 VL36 VL37 VL38 VL39 Output voltage VGMA16 VGMA16 + (VGMA15 - VGMA16) x 404 / 4288 VGMA16 + (VGMA15 - VGMA16) x 724 / 4288 VGMA16 + (VGMA15 - VGMA16) x 987 / 4288 VGMA16 + (VGMA15 - VGMA16) x 1211 / 4288 VGMA16 + (VGMA15 - VGMA16) x 1408 / 4288 VGMA16 + (VGMA15 - VGMA16) x 1585 / 4288 VGMA16 + (VGMA15 - VGMA16) x 1748 / 4288 VGMA16 + (VGMA15 - VGMA16) x 1900 / 4288 VGMA16 + (VGMA15 - VGMA16) x 2044 / 4288 VGMA16 + (VGMA15 - VGMA16) x 2182 / 4288 VGMA16 + (VGMA15 - VGMA16) x 2314 / 4288 VGMA16 + (VGMA15 - VGMA16) x 2441 / 4288 VGMA16 + (VGMA15 - VGMA16) x 2562 / 4288 VGMA16 + (VGMA15 - VGMA16) x 2680 / 4288 VGMA16 + (VGMA15 - VGMA16) x 2793 / 4288 VGMA16 + (VGMA15 - VGMA16) x 2903 / 4288 VGMA16 + (VGMA15 - VGMA16) x 3008 / 4288 VGMA16 + (VGMA15 - VGMA16) x 3110 / 4288 VGMA16 + (VGMA15 - VGMA16) x 3209 / 4288 VGMA16 + (VGMA15 - VGMA16) x 3305 / 4288 VGMA16 + (VGMA15 - VGMA16) x 3398 / 4288 VGMA16 + (VGMA15 - VGMA16) x 3488 / 4288 VGMA16 + (VGMA15 - VGMA16) x 3576 / 4288 VGMA16 + (VGMA15 - VGMA16) x 3661 / 4288 VGMA16 + (VGMA15 - VGMA16) x 3745 / 4288 VGMA16 + (VGMA15 - VGMA16) x 3826 / 4288 VGMA16 + (VGMA15 - VGMA16) x 3906 / 4288 VGMA16 + (VGMA15 - VGMA16) x 3985 / 4288 VGMA16 + (VGMA15 - VGMA16) x 4062 / 4288 VGMA16 + (VGMA15 - VGMA16) x 4138 / 4288 VGMA16 + (VGMA15 - VGMA16) x 4214 / 4288 VGMA15 VGMA15 + (VGMA14 - VGMA15) x 74 / 2065 VGMA15 + (VGMA14 - VGMA15) x 147 / 2065 VGMA15 + (VGMA14 - VGMA15) x 219 / 2065 VGMA15 + (VGMA14 - VGMA15) x 291 / 2065 VGMA15 + (VGMA14 - VGMA15) x 362 / 2065 VGMA15 + (VGMA14 - VGMA15) x 433 / 2065 VGMA15 + (VGMA14 - VGMA15) x 504 / 2065
NOTE: VSS219
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8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (9) Input data 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G/S VL40 VL41 VL42 VL43 VL44 VL45 VL46 VL47 VL48 VL49 VL50 VL51 VL52 VL53 VL54 VL55 VL56 VL57 VL58 VL59 VL60 VL61 VL62 VL63 VL64 VL65 VL66 VL67 VL68 VL69 VL70 VL71 VL72 VL73 VL74 VL75 VL76 VL77 VL78 VL79 Output voltage VGMA15 + (VGMA14 - VGMA15) x 574 / 2065 VGMA15 + (VGMA14 - VGMA15) x 644 / 2065 VGMA15 + (VGMA14 - VGMA15) x 713 / 2065 VGMA15 + (VGMA14 - VGMA15) x 782 / 2065 VGMA15 + (VGMA14 - VGMA15) x 851 / 2065 VGMA15 + (VGMA14 - VGMA15) x 919 / 2065 VGMA15 + (VGMA14 - VGMA15) x 987 / 2065 VGMA15 + (VGMA14 - VGMA15) x 1054 / 2065 VGMA15 + (VGMA14 - VGMA15) x 1120 / 2065 VGMA15 + (VGMA14 - VGMA15) x 1186 / 2065 VGMA15 + (VGMA14 - VGMA15) x 1251 / 2065 VGMA15 + (VGMA14 - VGMA15) x 1316 / 2065 VGMA15 + (VGMA14 - VGMA15) x 1380 / 2065 VGMA15 + (VGMA14 - VGMA15) x 1442 / 2065 VGMA15 + (VGMA14 - VGMA15) x 1504 / 2065 VGMA15 + (VGMA14 - VGMA15) x 1565 / 2065 VGMA15 + (VGMA14 - VGMA15) x 1625 / 2065 VGMA15 + (VGMA14 - VGMA15) x 1684 / 2065 VGMA15 + (VGMA14 - VGMA15) x 1742 / 2065 VGMA15 + (VGMA14 - VGMA15) x 1799 / 2065 VGMA15 + (VGMA14 - VGMA15) x 1854 / 2065 VGMA15 + (VGMA14 - VGMA15) x 1909 / 2065 VGMA15 + (VGMA14 - VGMA15) x 1962 / 2065 VGMA15 + (VGMA14 - VGMA15) x 2014 / 2065 VGMA14 VGMA14 + (VGMA13 - VGMA14) x 50 / 2368 VGMA14 + (VGMA13 - VGMA14) x 99 / 2368 VGMA14 + (VGMA13 - VGMA14) x 146 / 2368 VGMA14 + (VGMA13 - VGMA14) x 193 / 2368 VGMA14 + (VGMA13 - VGMA14) x 238 / 2368 VGMA14 + (VGMA13 - VGMA14) x 283 / 2368 VGMA14 + (VGMA13 - VGMA14) x 326 / 2368 VGMA14 + (VGMA13 - VGMA14) x 369 / 2368 VGMA14 + (VGMA13 - VGMA14) x 411 / 2368 VGMA14 + (VGMA13 - VGMA14) x 452 / 2368 VGMA14 + (VGMA13 - VGMA14) x 492 / 2368 VGMA14 + (VGMA13 - VGMA14) x 532 / 2368 VGMA14 + (VGMA13 - VGMA14) x 571 / 2368 VGMA14 + (VGMA13 - VGMA14) x 609 / 2368 VGMA14 + (VGMA13 - VGMA14) x 647 / 2368
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Table 2. Relationship between Input Data and Output Voltage Value (10) Input data 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G/S VL80 VL81 VL82 VL83 VL84 VL85 VL86 VL87 VL88 VL89 VL90 VL91 VL92 VL93 VL94 VL95 VL96 VL97 VL98 VL99 VL100 VL101 VL102 VL103 VL104 VL105 VL106 VL107 VL108 VL109 VL110 VL111 VL112 VL113 VL114 VL115 VL116 VL117 VL118 VL119 Output voltage VGMA14 + (VGMA13 - VGMA14) x 684 / 2368 VGMA14 + (VGMA13 - VGMA14) x 722 / 2368 VGMA14 + (VGMA13 - VGMA14) x 758 / 2368 VGMA14 + (VGMA13 - VGMA14) x 795 / 2368 VGMA14 + (VGMA13 - VGMA14) x 831 / 2368 VGMA14 + (VGMA13 - VGMA14) x 867 / 2368 VGMA14 + (VGMA13 - VGMA14) x 903 / 2368 VGMA14 + (VGMA13 - VGMA14) x 938 / 2368 VGMA14 + (VGMA13 - VGMA14) x 974 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1009 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1045 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1080 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1116 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1151 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1187 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1222 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1258 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1294 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1329 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1365 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1401 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1436 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1472 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1507 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1543 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1579 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1614 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1649 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1685 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1720 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1755 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1790 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1825 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1860 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1895 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1929 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1964 / 2368 VGMA14 + (VGMA13 - VGMA14) x 1998 / 2368 VGMA14 + (VGMA13 - VGMA14) x 2032 / 2368 VGMA14 + (VGMA13 - VGMA14) x 2066 / 2368
21
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Table 2. Relationship between Input Data and Output Voltage Value (11) Input data 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H 91H 92H 93H 94H 95H 96H 97H 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G/S VL120 VL121 VL122 VL123 VL124 VL125 VL126 VL127 VL128 VL129 VL130 VL131 VL132 VL133 VL134 VL135 VL136 VL137 VL138 VL139 VL140 VL141 VL142 VL143 VL144 VL145 VL146 VL147 VL148 VL149 VL150 VL151 VL152 VL153 VL154 VL155 VL156 VL157 VL158 VL159 Output voltage VGMA14 + (VGMA13 - VGMA14) x 2100 / 2368 VGMA14 + (VGMA13 - VGMA14) x 2134 / 2368 VGMA14 + (VGMA13 - VGMA14) x 2168 / 2368 VGMA14 + (VGMA13 - VGMA14) x 2201 / 2368 VGMA14 + (VGMA13 - VGMA14) x 2235 / 2368 VGMA14 + (VGMA13 - VGMA14) x 2268 / 2368 VGMA14 + (VGMA13 - VGMA14) x 2302 / 2368 VGMA14 + (VGMA13 - VGMA14) x 2335 / 2368 VGMA13 VGMA13 + (VGMA12 - VGMA13) x 33 / 2149 VGMA13 + (VGMA12 - VGMA13) x 66 / 2149 VGMA13 + (VGMA12 - VGMA13) x 100 / 2149 VGMA13 + (VGMA12 - VGMA13) x 133 / 2149 VGMA13 + (VGMA12 - VGMA13) x 166 / 2149 VGMA13 + (VGMA12 - VGMA13) x 199 / 2149 VGMA13 + (VGMA12 - VGMA13) x 232 / 2149 VGMA13 + (VGMA12 - VGMA13) x 266 / 2149 VGMA13 + (VGMA12 - VGMA13) x 299 / 2149 VGMA13 + (VGMA12 - VGMA13) x 332 / 2149 VGMA13 + (VGMA12 - VGMA13) x 365 / 2149 VGMA13 + (VGMA12 - VGMA13) x 399 / 2149 VGMA13 + (VGMA12 - VGMA13) x 432 / 2149 VGMA13 + (VGMA12 - VGMA13) x 465 / 2149 VGMA13 + (VGMA12 - VGMA13) x 498 / 2149 VGMA13 + (VGMA12 - VGMA13) x 532 / 2149 VGMA13 + (VGMA12 - VGMA13) x 565 / 2149 VGMA13 + (VGMA12 - VGMA13) x 598 / 2149 VGMA13 + (VGMA12 - VGMA13) x 632 / 2149 VGMA13 + (VGMA12 - VGMA13) x 665 / 2149 VGMA13 + (VGMA12 - VGMA13) x 698 / 2149 VGMA13 + (VGMA12 - VGMA13) x 732 / 2149 VGMA13 + (VGMA12 - VGMA13) x 765 / 2149 VGMA13 + (VGMA12 - VGMA13) x 798 / 2149 VGMA13 + (VGMA12 - VGMA13) x 831 / 2149 VGMA13 + (VGMA12 - VGMA13) x 864 / 2149 VGMA13 + (VGMA12 - VGMA13) x 897 / 2149 VGMA13 + (VGMA12 - VGMA13) x 930 / 2149 VGMA13 + (VGMA12 - VGMA13) x 963 / 2149 VGMA13 + (VGMA12 - VGMA13) x 996 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1029 / 2149
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Table 2. Relationship between Input Data and Output Voltage Value (12) Input data A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H C1H C2H C3H C4H C5H C6H C7H DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G/S VL160 VL161 VL162 VL163 VL164 VL165 VL166 VL167 VL168 VL169 VL170 VL171 VL172 VL173 VL174 VL175 VL176 VL177 VL178 VL179 VL180 VL181 VL182 VL183 VL184 VL185 VL186 VL187 VL188 VL189 VL190 VL191 VL192 VL193 VL194 VL195 VL196 VL197 VL198 VL199 Output voltage VGMA13 + (VGMA12 - VGMA13) x 1062 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1094 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1127 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1159 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1192 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1224 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1257 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1289 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1322 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1354 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1387 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1419 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1452 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1485 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1517 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1550 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1583 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1617 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1650 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1684 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1717 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1752 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1786 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1821 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1856 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1891 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1927 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1963 / 2149 VGMA13 + (VGMA12 - VGMA13) x 1999 / 2149 VGMA13 + (VGMA12 - VGMA13) x 2036 / 2149 VGMA13 + (VGMA12 - VGMA13) x 2073 / 2149 VGMA13 + (VGMA12 - VGMA13) x 2111 / 2149 VGMA12 VGMA12 + (VGMA11 - VGMA12) x 38 / 3080 VGMA12 + (VGMA11 - VGMA12) x 77 / 3080 VGMA12 + (VGMA11 - VGMA12) x 116 / 3080 VGMA12 + (VGMA11 - VGMA12) x 155 / 3080 VGMA12 + (VGMA11 - VGMA12) x 195 / 3080 VGMA12 + (VGMA11 - VGMA12) x 235 / 3080 VGMA12 + (VGMA11 - VGMA12) x 276 / 3080
23
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8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (13) Input data C8H C9H CAH CBH CCH CDH CEH CFH D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G/S VL200 VL201 VL202 VL203 VL204 VL205 VL206 VL207 VL208 VL209 VL210 VL211 VL212 VL213 VL214 VL215 VL216 VL217 VL218 VL219 VL220 VL221 VL222 VL223 VL224 VL225 VL226 VL227 VL228 VL229 VL230 VL231 VL232 VL233 VL234 VL235 VL236 VL237 VL238 VL239 Output voltage VGMA12 + (VGMA11 - VGMA12) x 316 / 3080 VGMA12 + (VGMA11 - VGMA12) x 357 / 3080 VGMA12 + (VGMA11 - VGMA12) x 399 / 3080 VGMA12 + (VGMA11 - VGMA12) x 440 / 3080 VGMA12 + (VGMA11 - VGMA12) x 482 / 3080 VGMA12 + (VGMA11 - VGMA12) x 524 / 3080 VGMA12 + (VGMA11 - VGMA12) x 566 / 3080 VGMA12 + (VGMA11 - VGMA12) x 609 / 3080 VGMA12 + (VGMA11 - VGMA12) x 651 / 3080 VGMA12 + (VGMA11 - VGMA12) x 694 / 3080 VGMA12 + (VGMA11 - VGMA12) x 738 / 3080 VGMA12 + (VGMA11 - VGMA12) x 782 / 3080 VGMA12 + (VGMA11 - VGMA12) x 826 / 3080 VGMA12 + (VGMA11 - VGMA12) x 871 / 3080 VGMA12 + (VGMA11 - VGMA12) x 916 / 3080 VGMA12 + (VGMA11 - VGMA12) x 962 / 3080 VGMA12 + (VGMA11 - VGMA12) x 1009 / 3080 VGMA12 + (VGMA11 - VGMA12) x 1057 / 3080 VGMA12 + (VGMA11 - VGMA12) x 1106 / 3080 VGMA12 + (VGMA11 - VGMA12) x 1157 / 3080 VGMA12 + (VGMA11 - VGMA12) x 1209 / 3080 VGMA12 + (VGMA11 - VGMA12) x 1263 / 3080 VGMA12 + (VGMA11 - VGMA12) x 1320 / 3080 VGMA12 + (VGMA11 - VGMA12) x 1379 / 3080 VGMA12 + (VGMA11 - VGMA12) x 1441 / 3080 VGMA12 + (VGMA11 - VGMA12) x 1506 / 3080 VGMA12 + (VGMA11 - VGMA12) x 1574 / 3080 VGMA12 + (VGMA11 - VGMA12) x 1647 / 3080 VGMA12 + (VGMA11 - VGMA12) x 1724 / 3080 VGMA12 + (VGMA11 - VGMA12) x 1805 / 3080 VGMA12 + (VGMA11 - VGMA12) x 1892 / 3080 VGMA12 + (VGMA11 - VGMA12) x 1983 / 3080 VGMA12 + (VGMA11 - VGMA12) x 2081 / 3080 VGMA12 + (VGMA11 - VGMA12) x 2184 / 3080 VGMA12 + (VGMA11 - VGMA12) x 2293 / 3080 VGMA12 + (VGMA11 - VGMA12) x 2409 / 3080 VGMA12 + (VGMA11 - VGMA12) x 2530 / 3080 VGMA12 + (VGMA11 - VGMA12) x 2658 / 3080 VGMA12 + (VGMA11 - VGMA12) x 2792 / 3080 VGMA12 + (VGMA11 - VGMA12) x 2933 / 3080
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Table 2. Relationship between Input Data and Output Voltage Value (14) Input data F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G/S VL240 VL241 VL242 VL243 VL244 VL245 VL246 VL247 VL248 VL249 VL250 VL251 VL252 VL253 VL254 VL255 Output voltage VGMA11 VGMA11 + (VGMA10 - VGMA11) x 154 / 4641 VGMA11 + (VGMA10 - VGMA11) x 314 / 4641 VGMA11 + (VGMA10 - VGMA11) x 482 / 4641 VGMA11 + (VGMA10 - VGMA11) x 659 / 4641 VGMA11 + (VGMA10 - VGMA11) x 846 / 4641 VGMA11 + (VGMA10 - VGMA11) x 1045 / 4641 VGMA11 + (VGMA10 - VGMA11) x 1260 / 4641 VGMA11 + (VGMA10 - VGMA11) x 1498 / 4641 VGMA11 + (VGMA10 - VGMA11) x 1768 / 4641 VGMA11 + (VGMA10 - VGMA11) x 2086 / 4641 VGMA11 + (VGMA10 - VGMA11) x 2482 / 4641 VGMA11 + (VGMA10 - VGMA11) x 3014 / 4641 VGMA11 + (VGMA10 - VGMA11) x 3825 / 4641 VGMA10 VGMA9
25
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ABSOLUTE MAXIMUM RATINGS
Table 3. Absolute Maximum Ratings (VSS1 = VSS2 = 0 V) Parameter Logic supply voltage Driver supply voltage Input voltage Output voltage Operating power dissipation Operation temperature Storage temperature Symbol VDD1 VDD2 VGMA1 - 16 Others DIO1, 2 Y1 - Y402 Pd Top Tstg CAUTIONS: If LSIs are stressed beyond those listed above "absolute maximum ratings", they may be permanently destroyed. These are stress ratings only, and functional operation of the device at these or any other condition beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Turn on power order: VDD1 control signal input VDD2 VGMA1 - VGMA16 Turn off power order: VGMA1 - VGMA16 VDD2 control signal input VDD1 Ratings -0.3 to 5.0 -0.3 to 16 -0.3 to VDD2+0.3 -0.3 to VDD1+0.3 -0.3 to VDD1+0.3 -0.3 to VDD2+0.3 300 (1) -20 to 75 -55 to 125 Unit V V V V mW C C
RECOMMENDED OPERATION CONDITIONS
Table 4. Recommended Operation Conditions (Ta = -20 to 75 C, VSS1 = VSS2 = 0 V) Parameter Logic supply voltage Driver supply voltage Gamma corrected voltage Driver part output voltage Maximum clock frequency (Single edge/Double edge) Output load capacitance Symbol VDD1 VDD2 (1) VGMA1 - VGMA8 VGMA9 - VGMA16 Vyo fmax CL
(1)
Min. Typ. 2.5 3.3 8.0 12.0 0.5 VDD2 VSS2 + 0.1 VSS2 + 0.1 VDD1 = 2.5 V VDD1 = 3.0 V 2
Max. 3.6 15.0 VDD2 - 0.1 0.5 VDD2 VDD2 - 0.1 55 / 40 75 / 55 200
Unit V V V V V MHz pF / PIN
NOTE: 1. Relationship between TFT-LCD panel and Pd (Pd CL * (VDD2) * fCLK1)
TFT-LCD panel standard SXGA UXGA & WUXGA
CL = 140pF max. VDD2 = 15 V max. VDD2 = 14 V
CL = 200pF max. VDD2 = 13 V max. VDD2 = 12 V
26
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
DC CHARACTERISTICS
Table 5. DC Characteristics (Ta = -20 to 75 C, VDD1 = 2.5 to 3.6 V, VDD2 = 8 to 15 V, VSS1 = VSS2 = 0 V) Parameter High level input voltage Low level input voltage Input leakage current High level output voltage Low level output voltage Resistor Symbol VIH VIL IL VOH VOL R0 R254 IVOH Driver output current IVOL Output voltage deviation Output RMS voltage deviation Output voltage range Logic part dynamic current Driver part dynamic current VO dVrms(2) Vyo IDD1 IDD2 Condition SHL, CLK2, D00 - D57, CLK1, SELT, DATPOL1, DATPOL2, DEC, POL, DIO1 (DIO2) DIO1 (DIO2), IO = -1.0 mA DIO1 (DIO2), IO = +1.0 mA Refer to Table 1. Resistor Strings VDD2 = 10.0 V, Vx = 3.5 V, Vyo = 9.5 V(1) VDD2 = 10.0 V, Vx = 6.5 V, Vyo = 0.5 V(1) VSS2 + 0.1 V to VDD2 - 1.5 V VDD2 - 1.5 V to VDD2 - 0.1 V Input data: 00H to FFH Input data: 00H to FFH VDD1 = 3.0 V (3) VDD2 = 10 V (4) Min. 0.8 VDD1 0 -1 VDD1 - 0.5 Rn x 0.7 1.0 VSS2 + 0.1 -2.0 2.0 7 10 3 4.0 10.0 Typ. Max. VDD1 0.2 VDD1 1 0.5 Rn x 1.3 -1.0 15 20 10 VDD2 - 0.1 7.0 mA 15.0 V mA mA Unit V A V
mV
NOTES: 1. Vyo is the output voltage of analog output pins Y1 to Y402. Vx is the voltage applied to analog output pins Y1 to Y402. 2. dVrms is a maximum deviation value from ideal difference between high output and low output at the same gray scale. 3. CLK1 period is defined to be 15.6 s at fCLK2 = 54 MHz, DEC = L, data pattern = 10101010 (checkerboard pattern), Ta = 25 C. 4, Yout Load Condition
2k YOUT
4k
4k
20pF
40pF
20pF
VCOM = 0.5 VDD2
2k
4k
4k
Figure 5. Yout Load Condition
27
S6C0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
SINGLE EDGE AC CHARACTERISTICS
Table 6. AC Characteristics (Ta = -20 to 75 C, VDD2 = 8 to 15 V, VSS1 = VSS2 = 0 V, DEC = L) Parameter Clock pulse width Clock pulse low period Clock pulse high period Data setup time Data hold time Start pulse setup time Start pulse hold time DATPOL-CLK2 setup time DATPOL-CLK2 hold time Start pulse delay time CLK1 setup time Driver output delay time1 Driver output delay time2 CLK1 pulse high period Data invalid period Last data timing CLK1-CLK2 time POL-CLK1 time Symbol PWCLK PWCLK(L) PWCLK(H) tSETUP1 tHOLD1 tSETUP2 tHOLD2 tSETUP4 tHOLD4 tPLH1 tSETUP3 tPHL1 tPHL2 PWCLK1 tINV tLDT tCLK1-CLK2 tPOL-CLK1 Condition CL = 20 pF PWCLK1 = 1 s, Refer Figure 5. Yout Load Condition CLK1 or CLK2 POL or CLK1 VDD1 = 2.5 to 3.0 V Min. 18 3 3 3 0 3 0 3 0 2 (3CLK2)
VDD1 = 3.0 to 3.6 V Min. 13 2 2 2 0 2 0 2 0 2 (3CLK2)
Unit
Max. 15 4 8 2 -
Max. 11 4 8 2 CLK2 period ns ns s CLK2 period
ns
1 1 8 8
1 1 6 6
28
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670
DOUBLE EDGE AC CHARACTERISTICS
Table 7. AC Characteristics (Ta = -20 to 75 C, VDD2 = 8 to 15 V, VSS1 = VSS2 = 0 V, DEC = H) Parameter Clock pulse width Clock pulse low period Clock pulse high period Data setup time Data hold time Start pulse setup time Start pulse hold time DATPOL-CLK2 setup time DATPOL-CLK2 hold time Start pulse delay time CLK1 setup time Driver output delay time1 Driver output delay time2 CLK1 pulse high period Data invalid period Last data timing CLK1-CLK2 time POL-CLK1 time Symbol PWCLK PWCLK(L) PWCLK(H) tSETUP1 tHOLD1 tSETUP2 tHOLD2 tSETUP4 tHOLD4 tPLH1 tSETUP3 tPHL1 tPHL2 PWCLK1 tINV tLDT tCLK1-CLK2 tPOL-CLK1 Condition CL = 20 pF PWCLK1 = 1 s , Figure 5. Yout Load Condition CLK1 or CLK2 POL or CLK1 VDD1 = 2.5 to 3.0 V Min. 25 4 4 4 0 4 0 4 0 1 (3CLK2)
VDD1 = 3.0 to 3.6 V Min. 18 3 3 3 0 3 0 3 0 1 (3CLK2)
Unit
Max. 15 4 8 2 -
Max. 15 4 8 2 CLK2 period ns ns s CLK2 period
ns
0.5 1 8 8
0.5 1 6 6
29
30
PWCLK tINV 1st tHOLD1 VIH VIL LAST-1 LAST PWCLK(L) PWCLK(H) INVALID DATA tSETUP4 tHOLD4 tSETUP1 1st DATA tSETUP2 tHOLD2 tPLH1 tSETUP3 PWCLK1 tPHL1 Target output voltage 90% Target output voltage tPHL2 HI-Z tLDT tCLK1-CLK2 0.5VDD1 LAST DATA tPOL-CLK1 INVALID DATA
S6C0670
CLK2
DXX
DATPOL1 DATPOL2
DIO1 input (DIO2 input)
DIO2 output (DIO1 output)
CLK1
SINGLE EDGE WAVEFORMS (VIH = 0.8 VDD1, VIL = 0.2 VDD1)
Figure 6. Waveforms, DEC = L
Y(1:402)
CLK2
CLK1
DXX
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
POL
PWCLK PWCLK(L) LAST-2 LAST-1 LAST tINV 1st tHOLD1 2nd PWCLK(H) VIH VIL
CLK2
DXX
INVALID DATA tSETUP4 tHOLD4
tSETUP1 1st DATA
DATPOL1 DATPOL2
tSETUP2 tHOLD2
DIO1 input (DIO2 input)
tPLH1
DIO2 output (DIO1 output)
tSETUP3 PWCLK1 tPHL1 Target output voltage 90%
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
CLK1
Y(1:402) tPHL2 HI-Z
DOUBLE EDGE WAVEFORMS (VIH = 0.8 VDD1, VIL = 0.2 VDD1)
Figure 7. Waveforms, DEC = H
tLDT tCLK1-CLK2 0.5VDD1 tSETUP1 LAST DATA tPOL-CLK1 tHOLD1 INVALID DATA
Target output voltage
CLK2
CLK1
DXX
POL
S6C0670
31
32
0.5VDD1 1/2CLK2 (DEC = H ) 2CLK2(Min.) tLDT Nth DATA INVALID DATA blanking time = Min. 4CLK2 First data in the next line 1st DATA 2nd DATA HI-Z HI-Z HI-Z HI-Z VGMA1 - VGMA8 VGMA9 - VGMA16 VGMA1 - VGMA8 VGMA9 - VGMA16 Charge sharing period
S6C0670
CLK2
DIO1 input (DIO2 input)
CLK1
DXX
N-1th DATA
Last data
RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD
Figure 8. Waveforms
VGMA1- VGMA8 VGMA9 - VGMA16
CLK1
POL
Y2N-1:odd number output
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
Y2N:even number output

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